The present invention relates to a real time signal processor for applying such digital signal processing techniques as digital filtering or high efficiency encoding to television signals and other video signals and, more particularly, to a processor for parallel processing of a frame of video signals with a plurality of unit processors.
Advantages of real time digital signal processing (DSP) include that it makes possible a filter or a modulator/demodulator with such a high degree of precision or stability as is impossible with analog techniques and that it lends itself to ready actualization of a time variant-adaptive filter and the like which is unthinkable with analog signal processing. Further by utilizing the attainments in digital LSI (large scale integration) technology which is now quickly advancing, it is made possible to reduce both the size and power consumption of real time DSP circuits, resulting in steady progress of the digital substitution for analog circuits and the application of such circuits to functionally more sophisticated purposes.
For all its remarkable advantages, DSP has its own disadvantage of requiring an enormous amount of arithmetic operations. For real time signal processing, a given digital signal has to be processed within the sampling period. For example if telephone speech (sampled at 8 kHz) is to undergo fourth-order recursive digital filtering, there will be required eight multiplications and eight additions in 125 microseconds. Therefore, processing of video signals, such as television signals, which are at least 1,000 times as wide in frequency range as and therefore have a sampling period of 1/1000 or even less of that of telephone speech signals, needs a circuit operable at least 1,000 times as fast as one for processing telephone speech signals.
For this reason, sophisticated DSP is at present limited to signals in the audio region, and video signals permit DSP only at a very simple stage.
In digital processing of audio signals, various parameters are altered or the signal processing algorithm is partially modified to achieve high speed DSP. Consequently, there is a strong demand for signal processors permiting alteration of the algorithm or parameters with software. Known instances of hardware achieving DSP with software include a signal processor described in the IEEE Journal of Solid-State Circuits, Vol. SC-16, No. 4, August 1981, pp. 372-376 (Reference 1). Among typical applications of this signal processor is a 32 kbps (kilobits per second) ADPCM coder described in the Proceedings of International Conference on Acoustics Speech of Signal Processing, published by the IEEE in 1982, pp. 960-963 (Reference 2), which is also intended for the processing of telephone speech.
The operating speed of a processor of this type cannot be readily increased by 1,000 times or more however fast its arithmetic circuit may be. Hence there is a zealous call for a software-controlled processor capable of real time DSP of video signals as sophisticated as of audio signals.
Meanwhile, for the real time processing of static pictures, instead of moving pictures, a parallel image processor is disclosed in the Japanese Patent Disclosure No. 53964/1984, which was laid open to public inspection by the Japanese Patent Office on Mar. 28, 1984. This parallel image processor basically comprises a plurality of processor modules, each consisting of a local memory and a local processor, and a supervisory processor connected by a bus to the processor modules and intended to control and supervise the processor modules. In processing a given frame, the supervisory processor supplies each processor module via the bus with video data in each of the blocks into which the frame is divided in a lattice pattern, and each processor module stores in its local memory a predesignated block and adjoining blocks, and processes the data stored into the local memory. The processed data are returned to the supervisory processor from each processor module via the bus.
In this parallel image processor, each processor module uses the data of not only the block to be processed but also the adjoining blocks, and therefore requires no communication with other processor modules in its video processing operation. Each processor module accordingly is able to accomplish convolution or correlation operation independently and highly accurately.
Yet, real time processing of video signals is difficult even for this parallel image processor. In the parallel image processor, too, once a video signal is written into the memory of its supervisory processor, and then read out for transfer to the individual processor modules The data processed by the processor modules are again transferred to the memory of the supervisory processor, and a processed video signal is obtained by reading the data out of this memory, resulting in an extremely long delay time, which makes real time operation difficult.